AbstractThe paper describes a structured communication link design technique, wave-pipelined interconnect, for networks-on-chip. We achieved 3.45GHz pipeline frequency and 55.2Gbps throughput on a 10mm 16bit interconnection in a 0.25um process. It uses 0.079mm2 of area, and it only needs 18.8pJ to transmit one bit. We reduce 79% crosstalk by using two techniques. This paper shows the various techniques we used to save power and area and achieve high performance in a relative old process in detail. Wave-pipelined interconnect design is easy and fully digital. Its many useful features give a large and flexible design space for high-performance chips.Note: "on-chip networks" and "communications link design" are more suitable for our paper.
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