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Keynote Speakers
 Wednesday, August 23 8:45 - 9:45 am Next Generation Networking for Parallel Systems Rama K Govindaraju Distinguished Engineer, IBM Corporation High Performance Computing Systems. ABSTRACT In this discussion, we will start with an outline of high level overview of the advances in parallel systems architecture as it relates to networking over the last decade along with current trends. We will discuss some of the fundamental challenges and choices confronting the industry today with respect to the system architecture and networking. We will bring to light some of the debates that have been raging in academia and the industry over the direction for networking, the protocols, the APIs, onloading/offloading and comment on potential root causes for the confusion. We will conclude the discussion with a high level sketch of a vision of where computer networking architecture should be heading and what the technical challenges are that will need to be addressed to ensure that computers of the future have the capability to address the next generation of grand challenge applications. BIO Dr. Rama K Govindaraju is currently a Distinguished Engineer at IBM's High Performance Computing Systems Lab and is responsible for the architecture of all HPC software components. Dr. Govindaraju is also the lead software person for the IBM PERCS project which is IBM's initiative in response to the HPCS project. Prior to his current assignments, Dr. Govindaraju has led the development of four generations of communications architecture for IBM's high performance computing systems since 1995 and has also held positions as the lead for IBM's UNIX architecture and design council. Dr. Govindaraju is a master inventor at IBM and is the author (co-author) of over 20 patents that have been awarded. Dr. Govindaraju is a senior member of the IEEE. Dr. Govindaraju received his BE in Computer Science from BIT, Ranchi, in 1988. Subsequently he received his MS and PhD in Computer Science from RPI, New York, in 1990 and 1994 respectively. |
 Thursday, August 24 8:45 - 9:45 am Requirements for Programming Modern FPGA Platforms Ivo Bolsens Vice President and Chief Technical Officer , Xilinx ABSTRACT Modern FPGA platforms have capabilities that are well suited to assume a central role in the implementation of complex embedded systems. Today the design flow for FPGA has been largely characterized by a hardware centric approach. We will argue that there are many additional opportunities for mapping complex applications to these FPGA platforms. The requirement is the exposure of the high computational efficiency of FPGAs matched by high bandwidth concurrent memory access and rich on-chip interconnectivity, combined with complete programmability. These requirements make FPGAs well suited for efficient implementation of signal processing, packet processing and high performance computing applications. We will discuss different domain specific programming environments that rely on flexible and soft template architectures, represented by API’ s that match the characteristics of a specific application domain. Next, system design flows compile high level programming constructs on these soft architectures that efficiently harness the intrinsic hardware capabilities of the FPGA platform. The soft architecture abstracts the detailed hardware implementation and facilitates scalable solutions, matching differently resourced FPGA devices to differing performance and sophistication requirements for packet processing or signal processing or high performance computing. This approach leads to a new breadth of system centric programming tools for FPGAs. BIO Ivo Bolsens joined Xilinx in June 2001 as vice president and chief technology officer (CTO). He is responsible for identifying Xilinx technologies and talent as well as heading up the Xilinx Research Laboratories, which focus on advanced research in the area of programmable logic. Mr. Bolsens came to Xilinx from the Belgium-based research center IMEC, where he was vice president of information and communication systems. He began there in 1984, holding various positions of increasing responsibility. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens earned his master's degree in electrical engineering and his Ph.D. in applied science from the Catholic University of Leuven in Belgium. He is author and co-author of more than 100 papers in the field of VLSI design, CAD, embedded system design, and wireless communication. He is also co-author of the book, "High Level Synthesis for Real Time Digital Signal Processing." |
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