IEEE Hot Interconnects Panel Discussion
Protocol off-loading vs on-loading in high-performance networks

Panelist Bios:

PATRICK GEOFFRAY
Patrick Geoffray earned his Ph.D. at the University of Lyon, France, in 2001. He is currently a Senior Software Architect at Myricom, in the Software Development Lab in Oak Ridge, TN. He is responsible for the firmware of Myrinet Express (MX) and he was previously in charge of various middlewares running on GM/Myrinet such as MPICH-GM and VIA-GM.

DIEGO CRUPNICOFF
Diego Crupnicoff is a Senior Architect with Mellanox Technologies. Diego has been with Mellanox since its inception in 1999 and has driven chip and system architectures for 4 generation of Mellanox products. He has been a member of the InfiniBand Trade Association Link Working Group from its very early days, actively participates in the Electromechanical Working Group and currently co-chairs the IBTA Technical Working Group. Diego holds several patents in the area of computer networks and systems architecture. Diego holds a B.Sc.in Computer Engineering (Summa Cum Laude) and an M.Sc.in EE. (Summa Cum Laude) both from the Technion - Israel Institute of Technology.

JEFF MOGUL
Jeff Mogul is a HP Labs Fellow; he has worked for DEC, Compaq, and HP research since 1986, on network and operating systems issues for high-performance computer systems, and on improving performance of the Internet and the World Wide Web. Jeff is an ACM Fellow, a co-author of the HTTP/1.1 standard and many others, and currently is Program co-chair for the 7th Symposium on Operating Systems Design and Implementation (OSDI).

LLOYD DICKMAN
Lloyd Dickman is CTO of QLogic’s System Interconnect Group. He was previously a Distinguished Architect at PathScale (acquired by QLogic), working on performance oriented interconnects. For many years, he headed the computer systems architecture and product planning groups at Amdahl where he directed the architecture and planning of several successful computer lines. Prior to that, he headed the computer systems architecture research group at DEC. His background includes work on instruction set design, multiprocessor structures, secure computing, virtual machine architectures, system software and VLSI design. He has held adjunct teaching positions at Berkeley, Northwestern, San Francisco State, Lowell and Northeastern.

GREG REGNIER
Greg Regnier is a Principal Engineer in Intel’s Systems Technology Lab. His experiences include the development of message passing sub-systems on the Intel Delta and Paragon supercomputers. Greg was a key contributor to the Virtual Interface Architecture that defined an industry standard interface for high performance cluster interconnects. He contributed to research that led to the development of Intel’s I/O Acceleration Technology (I/OAT), and co-authored a paper on “TCP On-loading for Data Center Servers” for IEEE Computer.

GARY MONTRY
Gary Montry is the Senior Scientist at NetEffect, Inc, a fabless semiconductor company based in Austin Texas. He is also the president of his own software company which specializes in bioinformatics software for pharmaceutical and biotech companies.

In 1988 Mr. Montry was awarded the first Gordon Bell award for parallel processing achievements. As a member of the technical staff at Sandia National Laboratories Mr. Montry was the first person to successfully parallelize a simulation code for a 1024 processor hypercube multicomputer. His team was the first ever to demonstrate 1000+ speedup of a computer code on a massively parallel multicomputer. Mr. Montry has authored several technical papers in the area of parallel processing for Fluid Dynamics and Electromagnetic applications. He has received several awards in the area of parallel processing for his achievements.