IEEE Hot Interconnects | Stanford University

SPONSORED BY

TECHNICAL
CO-SPONSORSHIP

TC on Scalable
Computing
(TCSC)

TC on Computer Architecture
(TCCA)

TC on High Speed Networking (TCHSN)

TC on Communications Switching and Routing (TCCSR)

TC on Optical Networking
(ONTC)

GOLD PATRONS

SILVER PATRONS

SISTER
CONFERENCES

CONTRIBUTORS

Panel Title: Multicore Interconnect: Scale-Up or Melt-down?

Moderator: Dan Pitt, Director, Vquence Pty. Ltd.

Panelists:
Charlie Janac, President and CEO, Arteris
Arun Sharma, Performance Engineering, Google
Manu Thapar, Vice President, Platform Engineering, Yahoo
Drew Wingard, CTO, Sonics

Abstract:
As we anticipate 32, 64, 100+ processors on a single chip, the problem of interconnecting the cores looms as a potential showstopper to scaling. Are we heading for the cliff here, or will our panelists bring visions of interconnect architectures, especially those that work on-chip but not between chips, that will enable the scaling to continue?

PROGRAM

Advanced Program

Registration CLOSED

KEYNOTE

Alex Dickinson [bio]
Luxtera

Tryggve Fossum [bio]
Intel

PRESS

EE Times article
07/30/07
Stanford confabs explore multi-core CPUs, nets