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  Tuesday
August 26, 2008
TUTORIALS
Wednesday
August 27, 2008
SYMPOSIUM
Thursday
August 28, 2008
SYMPOSIUM
7:30 am  

Continental Breakfast
Registration Open
Check-in/Register for Symposium

All Presentation Slides (click here)

Continental Breakfast
Registration Open
Check-in/Register for Symposium
7:45 am
8:00 am
8:15 am
SESSION 4
NETWORK PROCESSING
Session Chair: John Lockwood (Stanford University)
An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup
Socrates Demetriades (University of Pittsburgh, USA); Michel Hanna
(University of Pittsburgh, USA); Sangyeun Cho (University of Pittsburgh, USA); Rami Melhem (University of Pittsburgh, USA)

Constraint Repetition Inspection for Regular Expression on FPGA
Miad Faezipour (University of Texas at Dallas, USA); Mehrdad Nourani (University of Texas at Dallas, USA)
Network processing on SPE core in Cell Broadband
Yuji Kawamura (Sony Computer Entertainment Inc., Japan); Takeshi Yamazaki (Sony Computer Entertainment Inc., Japan); Hiroshi Kyusojin (Sony Corporation, Japan); Tatsuya Ishiwata (Sony Computer Entertainment Inc., Japan); Kazuyoshi Horie (Sony Computer Entertainment Inc., Japan)
8:30 am OPENING REMARKS
John Lockwood , General Chair
Fabrizio Petrini, Program Co-Chair
Ron Brightwell, Program Co-Chair
8:45 am
SESSION 1
ON-CHIP INTERCONNECTS
Session Chair: Fabrizio Petrini
A High-Speed Optical Multi-drop Bus for Computer Interconnections
Michael Tan (Hewlett Packard Company, USA); Paul Rosenberg (Hewlett Packard Laboartories, USA); Jong-Souk Yeo (Hewlett Packard Company, USA); Moray McLaren (Hewlett Packard Laboratories, USA); Terrel Morris (Hewlett Packard Company, USA)
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
Tushar Krishna (Princeton University, USA); Amit Kumar (Princeton University, USA); Patrick Chiang (Oregon State University, USA); Mattan Erez (The University of Texas at Austin, USA); Li-Shiuan Peh (Princeton University, USA)
Building manycore processor-to-DRAM networks with monolithic silicon photonics
Christopher Batten (Massachusetts Institute of Technology, USA); Ajay Joshi (Massachusetts Institute of Technology, USA); Jason Orcutt (Massachusetts Institute of Technology, USA); Anatoly Khilo (Massachusetts Institute of Technology, USA); Benjamin Moss (Massachusetts Institute of Technology, USA); Charles Holzwarth (Massachusetts Institute of Technology, USA); Milos Popovic (Massachusetts Institute of Technology, USA); Hanqing Li (Massachusetts Institute of Technology, USA); Henry Smith (Massachusetts Institute of Technology, USA); Judy Hoyt (Massachusetts Institute of Technology, USA); Franz Kärtner (Massachusetts Institute of Technology, USA); Rajeev Ram (Massachussetts Institute of Technology, USA); Vladimir Stojanovic (Massachusetts Institute of Technology, USA); Krste Asanovic (UC Berkeley, USA)
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
Michele Petracca (Politecnico di Torino, Italy); Benjamin Lee (Columbia University, USA); Keren Bergman (Columbia University, USA); Luca Carloni (Columbia University, USA)
9:00 am
9:15 am
9:30 am 15 MINUTE RECESS
9:45 am
SESSION 5
INDUSTRY TALKS I
Session Chair: Dennis Abts (Google)
Telecentric Optics for Free-Space Optical Link
Huei Pei Kuo (Hewlet Packard, USA); Michael Tan (Hewlett Packard Company, USA)
A Network Fabric for Scalable Multiprocessor Systems
Matthew Reilly (SiCortex, Inc, USA)
HPP Switch: A Novel High Performance Switch for HPC
Dawei Wang (Institute of Computing Technology Chinese Academy of Science, P.R. China)
10:00 am
10:15 am AM BREAK (10:15 - 10:45)
10:30 am AM BREAK (10:30 - 11:00)
10:45 am
SESSION 2
MEMORY SUBSYSTEM INTERCONNECTS
Session Chair: Luca Carloni (Columbia University)
Coherency Hub Design for Multi-Node Victoria Falls Server Systems
John Feehrer (Sun Microsystems Inc., USA); Paul Rotker (Sun Microsystems Inc,, USA); Paul Gingras (Sun Microsystems Inc., USA); Peter Yakutis (Sun Microsystems Inc., USA); Milton Shih (Sun Microsystems Inc., USA)
Low Power Passive Equalizer Design for Computer Memory Links
Ling Zhang (Univiversity of California, San Diego, USA); Wenjian Yu (Tsinghua University, P.R. China); Yulei Zhang (UCSD, USA); Renshen Wang (UCSD, USA); Alina Deutsch (IBM T.J.Watson Research Center, USA); George Katopis (IBM System Group, USA); Daniel Dreps (IBM System and Technology Group, USA); James Buckwalter (University of California @ San Diego, USA); Earnest Kuh (UC Berkeley, USA); Chung-Kuan Cheng (UCSD, USA)
OCDIMM:Scaling the DRAM Memory Wall Using WDM based Optical Interconnects
AMIT HADKE (University of California, Davis, USA); Tony Benavides (University of California, Davis, USA); Venkatesh Akella (University of California, Davis, USA); Rajeevan Amirtharajah (University of California, Davis, USA); Ben Yoo (University of California, Davis, USA)
11:00 am KEYNOTE 2
Mendel Rosenblum
Co-Founder and Chief Scientist, VMWare Inc; Professor, Computer Science, Stanford University


Interactions between Data Center Virtualization and Networking
11:15 am
11:30 am
11:45 am
12:00 pm LUNCH (12:00 - 1:00)
12:15 pm
12:30 pm
12:45 pm
1:00 pm
SESSION 3
ROUTING AND PERFORMANCE EVALUATION
Session Chair: Ron Brightwell (Sandia National Laboratories)
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation
Giorgos Dimitrakopoulos (Foundation for Research and Technology - Hellas (FORTH), Greece); Nikolaos Chrysos (Foundation for Research and Technology (FORTH), Greece)

High-speed, Short-latency Multipath Ethernet Transport for Interconnections
Nobuyuki Enomoto (NEC Corporation, Japan); Hideyuki Shimonishi (NEC, Japan); Junichi Higuchi (NEC Corporation, Japan); Takashi Yoshikawa (NEC Corporation, Japan); Atsushi Iwata (NEC Corporation, Japan)
Performance Analysis and Evaluation of PCIe 2.0 and Quad-Data Rate InfiniBand
Matthew Koop (The Ohio State University, USA); Wei Huang (The Ohio State University, USA); Karthik Gopalakrishnan (The Ohio State University, USA); Dhabaleswar Panda (The Ohio State University, USA)
Evaluation of an Integrated PCI Express IO Expansion and Clustering Fabric
Venkata Krishnan (Dolphin Inc., USA)
KEYNOTE 3
Distinguished Lecture
Dr. Eugen Schenfeld, IBM

Building practical exa bytes per second networks to interconnect the many core processors of the future
1:15 pm
1:30 pm
1:45 pm
2:00 pm
SESSION 6
INDUSTRY TALKS II
Session Chair: Dennis Abts (Google)
QsNetIII an Adaptively Routed Network for High Performance Computing
Duncan Roweth (Quadrics Ltd, United Kingdom); Trevor Jones (Quadrics Ltd, United Kingdom)
Adaptive Routing Strategies for Modern High Performance Networks
Patrick Geoffray (Myricom, USA); Torsten Hoefler (Indiana University, USA)
2:15 pm
2:30 pm PM BREAK (2:30 - 3:00)
2:45 pm
3:00 pm
TUTORIAL 1
OpenFlow
Brandon Heller, Stanford University; Guido Appenzeller, Stanford University; Nick McKeown, Stanford University

TUTORIAL 2

Designing HPC Clusters and Enterprise Datacenters: The InfiniBand and 10GE Way
Dhabaleswar Panda, Dr. Pavan Balaji, Argonne National Laboratory and University of Chicago
KEYNOTE 1
Executive Plenary Address
Andrew F. Bach, Senior Vice President NYSE/Euronext  

Network and Interconnect Requirements for Global
Equities Trading at NYSE/Euronext
PANEL DISCUSSION 3
Industry Forum Leaders: Optical Interconnects
Moderator: Prof. Luca Carloni, Columbia University

Panelists:
Ashok Krishnamoorthy
(Sun)
Madeleine Glick
(Intel)
Ray Beausoleil
(HP)
Jeff Kash
(IBM)

3:15 pm
3:30 pm
3:45 pm
4:00 pm PANEL DISCUSSION 1
Wall Street Roundtable
Requirements from the Trading Floor: Voices of the Experts

Moderator Daniel Pitt, National ICT Australia

Panelists:
Head Bubba
(Vice President, Credit Suisse)
David Cohen (Vice President, Storage Engineering, Goldman Sachs)
Peter Daniels
(Vice President, Windows Server Solutions, T. Rowe Price Associates)
Jacob Hall
(Vice President and Chief Architect, Wachovia Corporate and Investment Banking)
4:15 pm
4:30 pm CLOSING REMARKS

John Lockwood, General Chair
Fabrizio Petrini , IBM TJ Watson
Ron Brightwell, Sandia National Laboratories
4:45 pm PM BREAK (4:45 - 5:15) END SYMPOSIUM
5:00 pm
5:15 pm TUTORIALS CONTINUED
(5:15 - 7:00)
DINNER RECEPTION (5:15 - 6:30)
5:30 pm
5:45 pm
6:00 pm
6:15 pm
6:30 pm PANEL DISCUSSION 2
Industry Panel on Meeting Wall Street's Requirements 
Moderator Head Bubba, Credit Suisse

Panelists:
Frank Chism (HPC Technology Specialist, Microsoft)
Uri Cummings
(CTO & Founder, Fulcrum Microsystems)
Lloyd Dickman
, (CTO, Qlogic)
Dr. Cary Gunn (Co-Founder and CTO, Luxtera)
Michael Kagan
(Co-Founder and Vice President of Architecture, Mellanox)
Moiz Kohari (VP Engineering, Novell)
Asaf Somekh
(Director of Marketing, Voltaire)
David Taylor
(Senior Architect and Hardware Manager, Exegy)
J. Barry Thompson
(CTO & Founder, Tervela)
Sunay Tripathi, (Distinguished Engineer, Solaris Core Operating System, Sun Microsystems Inc.)
Bob Van Valzah (Director, Technical Marketing, 29West)

6:45 pm
7:00 pm END TUTORIALS
8:00 pm

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