| • |
Novel and innovative
interconnect architectures |
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Multicore processor interconnects |
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System-on-Chip Interconnects |
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Advanced chip-to-chip communication technologies |
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Optical interconnects |
| • |
Protocol and interfaces for interprocessor communication |
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Survivability and fault-tolerance of interconnects |
| • |
High-speed packet processing engines and network processors |
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System and storage area network architectures and protocols |
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High-performance host–network interface architectures |
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High-bandwidth and low-latency I/O |
| • |
Tb/s switching and routing technologies |
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Innovative architectures for supporting collective communication |
| • |
Novel communication architectures to support grid computing |
| • |
Requirements driving high-performance interconnects |
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| Submission
Guideline |
| • |
Submission deadline: extended to April 30, 2009 |
| • |
Notification of acceptance: May 31, 2009 |
| • |
Papers need
sufficient technical detail to judge quality and suitability for
presentation. Paper limit: 8 pages, two column. |
| • |
Submit title,
author, abstract, and full paper (eight pages, double-column, IEEE
format). |
| • |
Papers should
be submitted electronically at http://edas.info/N7355 for Hot Interconnects
17. |
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| About
the Conference |
| • |
Conference held
at Credit Suisse in New York City, NY. |
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Papers selected
will be published in proceedings by the IEEE Computer
Society. |
| • |
Presentations
are 30-minute talks in a single-track format |
| • |
Online information
at http://www.hoti.org |
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