IEEE Hot Interconnects | Wall Street

TUTORIAL 1
InfiniBand and 10-Gigabit Ethernet for Dummies
Dhabaleswar Panda (The Ohio State University), Pavan Balaji (Argonne National Laboratory), Matthew Koop (NASA Goddard)

Abstract & Bios: http://www.cse.ohio-state.edu/~panda/hoti09_t1.html

TUTORIAL 2
Designing High-End Computing Systems with InfiniBand and 10-Gigabit Ethernet
Dhabaleswar Panda (The Ohio State University), Pavan Balaji (Argonne National Laboratory), Matthew Koop (NASA Goddard)

Abstract: http://www.cse.ohio-state.edu/~panda/hoti09_t2.html

KEYNOTE 1
Title: The Other Face of On-Chip Interconnect

Anant Agarwal
Founder and CTO, Tilera Corporation

Abstract: The multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic structure of our software. The talk will borrow heavily from our experiences with on-chip interconnect in university research with the 16-core Raw multicore processor, in a commercial environment with Tilera's 64-core Tile processor, and in a future 1K-core multicore processor called ATAC that integrates optical and electrical interconnects.

Anant Agarwal is the Co-Founder and Chief Technology Officer of Tilera Corporation, a professor of Electrical Engineering & Computer Science at MIT, and a member of the CSAIL Laboratory. His teaching and research interests include computer architecture, VLSI, compilation, and software systems. Dr. Agarwal served as Associate Director of the MIT Laboratory for Computer Science (LCS) between 1998 and 2003, and is a co-leader of the Oxygen Project. He led a group that developed Sparcle (1992), an early multithreaded microprocessor based on the SPARC architecture, and the Alewife machine, a scalable shared-memory multiprocessor (1993). At MIT's CSAIL laboratory, Dr. Agarwal led the Raw project which developed a tiled multicore microprocessor for instruction level parallelism (ILP) and streams (2002). Anant also led the VirtualWires project at MIT. He has been a founder of several successful start-ups, including Virtual Machine Works, Inc. (1993).

Dr. Agarwal won the Maurice Wilkes prize for computer architecture in 2001, the Presidential Young Investigator award in 1991, and the Louis D. Smullin Award for teaching excellence at MIT in 2005. Dr. Agarwal holds a Bachelor Degree from IIT Madras and a Ph.D. in Electrical Engineering from Stanford University.

KEYNOTE 2
Title: The Need for Speed in Trading Environments

Spencer Greene
Chief Technology Officer, TIBCO Software

Abstract: Time is of the essence in today’s rapid business climate. The speed at which signals are transmitted and received at their destination is vital to optimizing the performance of real-time systems, both in hardware and in software. There is an industry shift taking place for mission critical low-latency systems with more functionality moving from software to hardware. In global financial trading environments, every microsecond, and soon every nanosecond, counts and can amount to tens of millions of dollars of lost market opportunities. We will speak about these changes and how predictive technologies are being used to create a competitive edge in today’s markets.

Spencer Greene is currently TIBCO Software Inc.’s Chief Technology Officer for the Financial Services Industry and the General Manager of TIBCO’s Global Exchange Business. In this role, he works closely with clients in banking, capital markets, exchanges and other related financial verticals, helping them solve their critical IT and business challenges using TIBCO technologies. Mr. Greene brings a wealth of financial expertise coupled with 25 years of experience in commercial software. His deep knowledge of investment, retail and commercial banking and its role in the global economy has directly benefited many of the world’s top banks. He is frequently called upon to discuss not only technology and architecture, but also business, regulatory and governmental issues concerning financial markets. Before re-joining TIBCO in 2004, he founded a hedge fund employing an automated trading solution based on a custom statistics algorithm he personally designed and implemented.

During his previous tenure with TIBCO Software, he managed the core development of the NASDAQ Europe stock exchange and as well as several derivative execution venues and various program and algorithmic trading systems. He also runs a small hedge fund that employs an automated trading solution based on a custom statistics algorithm he personally designed and implemented. He has worked onsite with Japanese, European and American banks on implementing their next generation SOA architectures. Mr. Greene’s background includes working as the general manager of the broadcast division at CJDS Systems, a company supplying software used in the purchase of 50% of all US television commercials. He has also written historical simulations games in assembler for the Japanese market, developed sales order and inventory tracking software, and coded a sophisticated application for analysis of temporomandibular joint anomalies.

On the personal side, Mr. Greene enjoys photography, linguistics, C++, and the study of quantitative trading models as well as haute couture fashion. An avid student of the world, he is highly conversant in Japanese and has studied many other foreign languages.

KEYNOTE 3
Title: High-speed networking and the race to zero

Andrew F. Bach
Senior Vice President, Technology for NYSE Euronext

Abstract: There may be no more critical an environment for interconnect and networking than the Electronic and trading floors of the NYSE Euronext markets. National economies can be impacted and personal fortunes created in the blink of an eye. At NYSE Euronext, we are leading the charge to ever faster and faster trading speeds through the adoption of leading edge technology and architectures. In this talk, we will outline the road ahead in the quest to zero execution times.

In this capacity, he is responsible for planning the company’s private fiber-optic network that links all NYSE, Securities Industries Automation Corporation (SIAC), which is a subsidiary of NYSE, and American Stock Exchange (AMEX) sites and the national networks SIAC operates.

Additionally, Mr. Bach is Head of Product Development for Secure Financial Transaction Infrastructure (SFTI) at SIAC. He oversees all aspects of the SFTI product line. Under his management, SFTI’s products and services have increased to include exchanges, market centers and industry utilities. It now offers a variety of financial service content providers to more than 600 firms, representing over 99% of nationally listed market order flows.

While at SIAC, Mr. Bach has held various positions, including Vice President of Communication Administration, Vice President of Architecture and Vice President of Project Engineering.

Prior to SIAC, Mr. Bach was the manager of software development at EDO Corporation where he developed advanced sonar signal processing equipment for the world’s navies.

Mr. Bach sits on the board of the Promise Fund at Polytechnic University in New York City, where he also is an adjunct professor for graduate studies in networking. He also is a member of the Nortel Customer Advisory Board, and the Wall Street Technology Association and is an active member of the Institute of Electrical and Electronic Engineers (IEEE) and the Association of Computer Machinery (ACM). Awards for Mr. Bach’s contribution to the industry include the prestigious ComputerWorld Smithsonian award in 2000 for his role in the integration of IP multicasting technology in the financial services industry. He also holds multiple patents in communications technologies. Mr. Bach received a Bachelor of Science in Electrical Engineering at the Pratt Institute.

Panel Discussion
Has the time come to promote Ethernet as a low latency, high throughput fabric interconnect?
Moderator: David Cohen

Abstract: The answer to this question hinges on support for RDMA-based Communication and this is the focus of our discussion. Motivated by FCoE requirements, enhancements to the Ethernet standard transform this unreliable media into one that can support lossless transmissions. This has motivated three distinct camps to come forward with conflicting proposals for an RDMA transport. All three see the host I/O adaptor and the message framing protocols as being at the heart of the challenge. Where they differ, however, is the extent to which the interconnect plays a role in the communication

SPECIAL SESSION
Industry Leader Forum
Session Chair: TBA

Abstract: Hot Interconnects comes to Wall Street where the bulls and bears of industry debate the value proposition of emerging low-cost optical networks. We've assembled a cross-section of industry, from optical components to systems and applications, to explore bottlenecks and bandwidth requirements, to discuss which metrics are most relevant for making engineering tradeoffs in real-world applications and which are the most appropriate optimization criteria. How do these tradeoffs differ for cluster networks up to, say, 100k nodes, versus wide area networks that span continents? These and other intriguing questions will be addressed.

We will hear from industry experts how emerging optical technology is changing the landscape of networking. From active optical transceivers to dense wave division multiplexing (DWDM), this group of industry leaders will help connect the dots and provide practical insight along the way.