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Keynote

Speaker

Sailesh Kottapalli
Intel Senior Fellow, Intel Architecture, Graphics and Software
Chief Architect, Datacenter Processor Architecture

Title

From Microns to Miles - The Broad Spectrum of Intel's Interconnect Technology Strategy

Abstract

The next generation of computing and communications use models requires a broad spectrum of interconnect technologies, spanning from microns to miles. Machine-generated data is driving explosive growth in wireless and datacenter traffic including massive growth in computing needs to derive insights from processing the ever-growing amount of data. Hyper-scale datacenters process internal traffic 5x greater than overall internal traffic with rich packet processing and low latency. Compute architecture is evolving with specialized high-bandwidth, low-latency interconnect among compute engines, accelerators, memory and IO with a need for advancement in the silicon level interconnect between IP blocks and within the package. Critical to this is the investment and leadership in software technology and ecosystem engagement, including Machine Learning Scaling Libraries and the Data Plane Development Kit.

Bio

Sailesh Kottapalli is an Intel Senior Fellow and the chief architect of data center processor architecture in the Intel Architecture Graphics and Software group. He leads a team of architects responsible for developing the architecture of Intel® Xeon® and Intel® Atom™ server product lines as well as the overall compute solutions strategy for datacenter segment. He also leads a cross-organizations effort in driving the technology leadership on the Interconnect pillar.

Kottapalli joined Intel in 1996 as a design engineer working on the first Intel® Itanium® processor, then code-named "Merced." Subsequently, he served as lead engineer for several Intel Itanium and Intel Xeon processor evaluations, and more recently, as lead architect for a series of Intel Xeon server processors. His work in this area earned Kottapalli an Intel Achievement Award for delivering record generational performance improvements in a high-end server product.

An active participant in industry and internal conferences, Kottapalli has authored or co-authored several published technical papers, delivered talks and taken part in roundtables and panel discussions. He has also been granted approximately three dozen patents in processor architecture, with additional patents pending.

Kottapalli holds a bachelor's degree in computer science from Andhra University in India and a master's degree in computer engineering from Virginia Tech.



Keynote

Speaker

Steve Scott
Senior Vice President and Chief Technology Officer
Cray Inc.

Title

Rosetta: A 64-port Switch for Cray's Slingshot Interconnect

Abstract

This talk will describe Rosetta, the switch at the core of Cray's next generation Slingshot interconnect. Rosetta is comprised of 64 ports, each providing 200 Gbps/direction over four lanes of 56G PAM4 SerDes. Rosetta enhances Ethernet with leading-edge HPC network functionality. It can connect to standard Ethernet endpoints and switches, but also implements an optimized "HPC Ethernet" protocol that provides several performance and resilience functions, including streamlined headers, credit-based flow control, low-latency FEC, link-level retry to tolerate transient failures, and lane-degrade capability to tolerate hard failures. Rosetta implements highly flexible QoS traffic classes, an adaptive routing mechanism capable of over 90% sustained network utilization at scale, a rich suite of synchronization mechanisms, and, most importantly, a novel congestion control mechanism suitable for dynamic HPC and datacenter workloads. Rosetta's congestion management provides strong performance isolation between workloads, and low, uniform packet latency, making it ideally suited for emerging heterogeneous, data-centric workloads. Tests using the new GPCNeT benchmark demonstrate its effectiveness.

Bio

Steve Scott serves as Senior Vice President and Chief Technology Officer, responsible for guiding the long-term technical direction of Cray's supercomputing, storage and analytics products. Dr. Scott rejoined Cray in 2014 after serving as principal engineer in the Platforms group at Google and before that as the senior vice president and chief technology officer for NVIDIA's Tesla business unit. Dr. Scott first joined Cray in 1992, after earning his Ph.D. in computer architecture and BSEE in computer engineering from the University of Wisconsin-Madison. He was the chief architect of several Cray supercomputers and interconnects. Dr. Scott is a noted expert in high performance computer architecture and interconnection networks. He holds 41 U.S. patents in the areas of interconnection networks, cache coherence, synchronization mechanisms and scalable parallel architectures. He received the 2005 ACM Maurice Wilkes Award and the 2005 IEEE Seymour Cray Computer Engineering Award, and is a Fellow of IEEE and ACM. Dr. Scott was named to HPCwire's "People to Watch in High Performance Computing" in 2012 and 2005.


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IMPORTANT DATES
(Papers)

Submission deadline
(extended):
May 17

Notification: June 7

IMPORTANT DATES (Tutorials)

Proposals due: May 10

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